The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved power switching stage architecture for a buck topology-based, DCxe2x80x94DC converter, which has an upper power switching N-channel device FET integrated in the same semiconductor circuit chip with the switching driver, while the lower power switching is also an N-channel FET, but is external to the driver chip. In addition, either or both of the two power switching FETs may be configured to include a pilot FET cell, to facilitate current sensing for the controller.
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current power sources, such as a buck-mode, pulse width modulation (PWM) based, DCxe2x80x94DC converter of the type diagrammatically shown in FIG. 1. As shown therein, a controller 10 supplies a synchronous PWM signal to a driver 20, for controlling the turn-on and turn-off of a pair of electronic power switching devices, that are external to the driver circuit 20 and to which a powered load 65 is coupled. In the illustrated DCxe2x80x94DC converter, the external electronic power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30, and a lower (or low side) power NFET device 40, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
The upper NFET device 30 is turned on and off by an upper gate switching signal UGATE applied to its gate from driver 20, while the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE supplied from driver 20. The gate drive voltage for the upper NFET device 30 may be driven directly from a source voltage higher than the voltage VIN, or may be bootstrapped as shown in FIG. 2. Also, rather than employ an NMOS device for the upper FET a PMOS device may be employed.
A common node 35 between the upper and lower power FETs is coupled through an inductor 50 to a load reservoir capacitor 60 that is coupled to a reference voltage terminal (GND). The connection 55 between inductor 50 and capacitor 60 serves as an output node 55 from which a desired (regulated) DC output voltage VOUT is applied to LOAD 65 (coupled to GND). The output node connection 55 is also fed back to error amplifier circuitry 12 within the controller 10. The error amplifier circuitry is used to regulate the converter""s output DC voltage relative to a reference voltage supply. In addition, the common node 35 between the controllably switched NFETs is coupled (by way of a feedback sense resistor 45) to current-sensing circuitry 15 within the controller 10, in response to which the controller adjusts duty ratio of the PWM signal, as necessary, to maintain the converter""s DC output within a prescribed set of parameters.
The current trend in DCxe2x80x94DC converters is to operate at relatively high switching frequencies (e.g., on the order of several KHz to one MHz or higher). This serves to reduce the size, and therefore cost and circuit board occupancy of the inductor and capacitor components coupled between the common node and the load. The increase in switching frequency, however, is not without a performance penalty, especially for relatively large voltage step down ratios (e.g., from a 12 VDC supply (as may be supplied from an automobile battery) to an output voltage on the order of 1.2-1.5 VDC). In such a case, the upper power FET (which typically operates a relatively low duty cycle (e.g., on the order of ten to twelve percent)) can introduce significant switching losses, particularly since it is an external device having substantial parasitic impedance. On the other hand, the lower FET operates at a relatively high duty cycle and does not suffer severe switching-based power dissipation.
One proposal to address this problem has been to integrate both the upper and lower FETS into a common integrated circuit chip with the driver, as diagrammatically illustrated in FIG. 4, which shows the both devices as N-channel devices, or as shown in FIG. 5 wherein the upper device is a P-channel device and the lower device is an N-channel device. A drawback to this approach is the considerable cost of manufacture of the resulting integrated circuit chip to accommodate both power switching devices. An alternative proposal, shown in FIG. 6, has been to integrate an upper P-channel device in the same chip as the driver, but leave the lower N-channel FET as an external device.
This approach has the advantage of reducing the switching losses associated with relatively low duty cycle of the upper FET, and also reducing costs of having to integrate both devices in a common circuit chip (and the fact that P channel devices are easier to implement from a gate drive standpoint). It also takes advantage of the fact that the lower NFET device operates at a relatively high duty cycle and its implementation is fairly well standardized.
Now, although the partially integrated approach of FIG. 6 provides an improvement over the fully external or fully integrated approaches of FIGS. 1-5, the use of a P-channel FET as the upper power switching device suffers from a considerably higher on-resistance and large silicon occupancy area.
In accordance with the present invention, the above shortcomings of conventional power switching stage topologies are substantially reduced by a new and improved architecture, comprised of an upper power switching N-channel device FET integrated in the same semiconductor circuit chip with the driver, while the lower power switching is also an N-channel FET, but is external to the driver chip. In addition, either or both of the two power switching FETs may be configured to include a xe2x80x98pilotxe2x80x99 FET cell, so as to facilitate current sensing for the controller.